Device interconnections in Very Large Scale Integrated (VLSI) or Ultra-Large Scale Integrated (ULSI) semiconductor chips incorporate multilevel interconnect wiring structures containing patterns of metal wiring layers called traces. Wiring structures within a given trace or level of wiring are separated by an intralevel dielectric, while the individual wiring levels are separated from each other by layers of an interlevel dielectric. Conductive vias are formed in the interlevel dielectric to provide interlevel contacts between the wiring traces.
By means of their effects on signal propagation delays, the materials and layout of these interconnect structures can substantially impact chip speed, and thus chip performance. Signal propagation delays are due to RC time constants wherein R is the resistance of the on-chip wiring, and C is the effective capacitance between the signal lines and the surrounding conductors in the multilevel interconnection stack. RC time constants are reduced by lowering the specific resistance of the wiring material, and by using interlevel and intralevel dielectrics (ILDs) with lower dielectric constants k.
A preferred metal/dielectric combination for low RC interconnect structures may be Cu metal with a dielectric such as SiO2 (k˜4.0). Due to difficulties in subtractively patterning copper, copper-containing interconnect structures are typically fabricated by a Damascene process. In a Damascene process, metal patterns inset in a layer of dielectric are formed by the steps of 1) etching holes (for vias) or trenches (for wiring) into the interlevel or intralevel dielectric, 2) lining the holes or trenches with one or more adhesion or diffusion barrier layers, 3) overfilling the holes or trenches with a metal wiring material, and 4) removing the metal overfill by a planarizing process such as chemical mechanical polishing (CMP), leaving the metal even or coplanar with the upper surface of the dielectric. The above process may be repeated until the desired number of wiring and via levels have been fabricated.
Fabrication of interconnect structures by Damascene processing can be substantially simplified by using a process variation known as Dual Damascene, in which patterned cavities for the wiring level and its underlying via level are filled in with metal in the same deposition step. This reduces the number of metal polishing steps by a factor of two, at substantial cost savings, but requires that a dual-relief pattern be introduced into the combined via and wiring level dielectric.
Low-k alternatives to the dielectric SiO2 include carbon-based solid materials such as diamond-like carbon (DLC), also known as amorphous hydrogenated carbon (a-C:H), fluorinated DLC (FDLC), SiCO or SiCOH compounds, and organic or inorganic polymer dielectrics. Nanoporous versions of SiO2 and these carbon-based materials have even lower k values, while air gaps have the lowest k values of any material where k˜1.00. The gas in the air gap may comprise air, any gaseous material or vacuum.
Examples of multilayer interconnect structures incorporating air gaps are described in U.S. Pat. No. 5,461,003, by R. H. Havemann and S-P Jeng; U.S. Pat. No. 5,869,880, by A. Grill and K. L. Saenger; and U.S. Pat. No. 5,559,055, by M. S. Chang and R. W. Cheung.
Air gaps can be formed by one of two basic methods. In the first method, described previously by J. G. Fleming et al. in Advanced Metallization and Interconnect Systems for ULSI Applications in 1996 p. 471–7 (1997) and shown in FIGS. 1A–1C herein, the air gap is formed in a structure comprising a cavity 10 between conductive features 20 on substrate 30 as shown in FIG. 1A. Air gaps or keyholes 40 are formed when cavity 10 is partially filled with a poorly conformal layer of dielectric 50 as shown in FIG. 1B. Poorly conformal dielectric 50 may be deposited by a process such as plasma-enhanced chemical vapor deposition (PECVD). FIG. 1C shows the structure of FIG. 1B after planarization by a process such as chemical mechanical polishing.
A second method for forming air gaps utilizes a sacrificial material which is removed after formation of a bridge layer, as illustrated in FIGS. 2A–2C herein and previously described in P. A. Kohl et al., Electrochemical and Solid-State Letters 1 49 (1998). FIG. 2A shows a planar structure comprising substrate 30, conductive features 20, and sacrificial material 60. The structure of FIG. 2A is then capped with a “bridge” layer 70 shown in FIG. 2B, followed by removal of sacrificial material 60 to leave air gap 80 as shown in FIG. 2C. Examples of sacrificial materials and removal methods include poly(methy methacrylate) (PMMA) and parylene (e.g., poly-para-xylylene sold under the trademark “Paralylene”) which may be removed by organic solvents, oxygen ashing, and/or low temperature (˜200° C.) oxidation, and norborene-based materials such as BF Goodrich's Unity Sacrificial Polymer™, which may be removed by low temperature (350–400° C.) thermal decomposition into volatiles. In the case of Unity™, the volatiles actually diffuse through the bridge layer. Diffusion through a bridge layer was demonstrated by Kohl et al. for structures comprising SiO2 (500 nm) bridge layers deposited by low temperature PECVD.
Compared to solid dielectrics, air gap dielectrics have lower thermal conductivity, near-zero mechanical strength, and higher permeability to moisture and oxygen. Workable schemes for incorporating air gaps into interconnect structures must take these limitations into account. A particular concern with air gap dielectrics is that they leave metal wiring features more susceptible to the opens and shorts induced by electromigration driven mass transport, since the wiring features are no longer dimensionally constrained by a solid dielectric in which they are embedded. Another concern is that structures with air gaps may not be as uniformly planar as structures built with intrinsically more rigid solid dielectrics. This can be a problem if locally depressed areas are formed by bridge layer sag over unsupported air gaps, since metal over or filling these areas will remain in the structure after CMP and be a source of shorts and/or extra capacitance.
It is thus an object of this invention to provide a multilayer interconnect structure containing air gaps.
It is a more specific object of this invention to provide a stable, high performance multilayer interconnect structure containing air gaps in the plane of one or more buried wiring levels to reduce wiring capacitance.
It is a further object of this invention to provide an air-gap-containing interconnect structure which is resistant to electromigration failure and environmental corrosion.
It is an additional object of this invention to provide a method for forming multilayer interconnect structures containing voids, cavities or air gaps in the plane of one of more buried wiring levels, using Dual Damascene processing and an air gap defined initially by a solid sacrificial material which is subsequently removed by thermal decomposition to form a gas which is out-diffused or released through openings or removed by plasma, O2, microwave radiation or by radiant energy such as by ultra violet light or by a laser at a selected wavelength.